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Chapter 3: Design Rules and Procedures
Hierarchical Design
Automatic flow—allows you to control the entire design process in the MATLAB
or Simulink environment with the Signal Compiler block. With this flow, your
design compiles inside a temporary Quartus II project. The results of the synthesis
and compilation display in the Signal Compiler Messages box. You can also use
the automatic flow to download your design into supported development boards.
Manual flow—you can also add the . mdl file to an existing Quartus II project
using the < model name >_add.tcl script. This script is generated whenever the
Signal Compiler or TestBench block is run. You can use the script to add the . mdl
file and any imported HDL to your project. You can then instantiate your design in
HDL.
Simulation flow—if the ModelSim executable ( vsim.exe ) is on your path, you can
use the TestBench block to compile your design for ModelSim simulation. You can
then automatically compare the Simulink and ModelSim simulation results.
For an example that uses the Signal Compiler blocker, refer to page 2–14 of the
“Getting Started” .
f For information about the parameters for the Signal Compiler and TestBench blocks,
refer to the AltLab Library chapter of the DSP Builder Reference Manual .
DSP Builder supports the Simulink Bus Creator, Bus Selector, and Bus Assignment
blocks but you must only use them for routing.
Hierarchical Design
DSP Builder supports hierarchical design using the Simulink Subsystem block.
DSP Builder preserves the hierarchy structure in a VHDL design and each hierarchical
level in a Simulink model file (. mdl ) translates into one VHDL file.
DSP Builder Handbook
Volume 2: DSP Builder Standard Blockset
November 2013 Altera Corporation
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